After providing a brief refresher on functional coverage basics, the paper went on to ask: “How do analog effects get captured in functional coverage while performing system level verification?” Since analog effects are described in form of floating point numbers, it becomes apparent that to meet the needs of mixed-signal in functional coverage, the language needs to support a floating point (aka real) data type. Since SystemVerilog is widely used in verification, we developed our proposal around the P1800-2009 standard of SystemVerilog.

The paper then went into the detailed mechanics of real typed SystemVerilog coverpoint objects. It highlighted an important extension to the language, specifically an instance-specific covergroup option called range_precision, to divide a range of vector bins into sub-ranges. It also explained how the existing features of SystemVerilog covergroup can be modified or extended with the introduction of real data type. Finally, the paper explored some of the challenges that are still open in the areas of floating point arithmetic and issues related to overflow and underflow. It drew a conclusion stating that our next step would be to complete an analysis of the Functional Coverage Section of the P1800 SystemVerilog Language Reference Manual (P1800-2012) and then work with the SV-EC sub-committee members for standardization of our proposal.

The audience was primarily filled with users from the digital verification community, and therefore there was a lot of curiosity in hearing a presentation coming from someone more oriented to the analog and mixed-signal world. An engineer from Dialog Semiconductor expressed strong interest in our work and stated that she found immediate use of this approach in her group’s verification initiatives. There was a concern raised by one member of the audience who wondered whether we’re trying to make the language more complex. We explained that the we were only proposing extensions that fill the gap between the existing integral type support to the desired level of real data type support.

There were some very good suggestions provided as part of audience feedback, such as consideration of logarithmic ranges and also support for the real data type for transition bins.Overall it was a very enriching experience for me and my colleagues to share our work with a community of folks who are certainly showing signs of interest to extend standard verification techniques to the wonderful world of analog. If you need further information on the presentation, please do not hesitate to contact me at prabal@cadence.com.

Prabal Bhattacharya

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital content in response to new functionality demands, and steady growth of IP blocks into larger and larger SoCs, traditional AMS verification flows are becoming inefficient in handling full chip verification. High performance digital verification and high accuracy analog verification represented the foundation for traditional AMS verification, characterized by performance and accuracy tradeoffs -- thus making AMS verification the biggest challenge facing verification engineers today.

Lack of consistent handoff between analog and digital design boundaries and the inexistence of mature verification methodologies for mixed signal verification have been common reasons for chip re-spins.  As AMS verification matures, so do the methodologies that support AMS verification which now include low-power, behavioral modeling abstraction, assertions, and metric driven verification methodologies.

I had the pleasure of meeting lots of customers during CDNLive! Silicon Valley 2012 and learned firsthand about their verification challenges and the approaches they're taking to address such challenges. Ken Luo from LSI Corporation delivered a presentation about real number model (RNM) development and application in mixed-signal SoC verification. Luo iterated that exploding operating modes, functionality demands for digital control, and calibration to mitigate against process variations are typical trends in modern SoC designs.

As such, analog simulation performance and convergence are bottlenecks for full chip verification. Luo discussed the benefits of adopting RNM, which include the continuous value and discrete time nature of real numbers that allow for pure digital solver simulation and high speed performance. Also, Luo highlighted other features like multiple drivers and resolution function support for RNM, discipline association, and ease of connecting real to electrical nets using R2E/E2R connect modules.

Luo also shared some guidelines for RNM modeling regarding signal flow modeling (voltage vs. current), sampling approaches (uniform vs. non-uniform sampling) which are required to balance performance and accuracy, and modeling data processing algebraic equations vs. nonlinear table models. One of the key takeaways of the presentation is to "model what you need and not what you can" to reflect the specified functionality and avoid unnecessary high order effects. Another takeaway is to align the model development plan with the design development plan, maintain consistent interfaces for model/design, and to use version control to keep the model/design in sync.

Also, Luo discussed that models should be classified according to the block characteristics and verification requirements. Communication I/Os that toggle frequently and have low accuracy requirements can be modeled using Verilog, while high accuracy and frequently toggling nodes like clocks, oscillators, and high bandwidth amplifiers or high accuracy, less frequently toggling nodes like reference voltage/current and, low speed high resolution ADC/DAC, should be modeled using Verilog-AMS/Wreal.

Luo introduced an LSI application, which is a hard disk drive (HDD) PreAmplifier that performs small signal amplification (during READ operation) and voltage waveform shaping (during WRITE operation) interfaces to the HDD R/W heads. The PreAmp has been historically an analog ASIC, but today it has became a complex mixed-signal SoC due to > 4.0 Gbps high data rate requirements, multiple operation modes, programmability of bias/threshold control and calibration. The increased feature complexity poses a challenge to AMS verification due to extremely long simulation times, D/A interface coverage and lack of coverage measurement.

The LSI verification team used Cadence verification planning (vPlan) to collect and define model feature requirements and align verification milestones. Also, the team developed analog mixed-signal Universal Verification Components (UVC) and checkers for analog signals for amplitude, frequency, common mode voltage and sampling frequency. The team observed significant improvements (~600x) using the RNM models over SPICE simulations, which suffered convergence issues and didn't provide adequate coverage. The RNM models achieved 95% accuracy, enabled full coverage, and achieved first silicon success with zero functional bugs.

AMS verification engineers need access to a strong design environment that bridges the productivity gap between analog and digital verification flows. The Virtuoso environment empowered by AMS Designer verification technology is well equipped to resolve the inconsistent handoff between analog and digital design boundaries. RNM makes it possible to apply advanced digital verification methodologies to mixed-signal SoCs and enhance traditional AMS verification.

If you need further information on the presentation, please do not hesitate to contact me at ahmedelz@cadence.com

Ahmed Elzeftawi

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels.

Unfortunately, compared with the advancement of digital designs over the past decade, the state of art analog design is significantly lagging behind. For example, the throughput of microprocessors doubles every 1.5 years while it takes three times longer to achieve the same advancement for analog designs. Another big roadblock for analog designs is the power consumption. According to Boris Murmann, professor at Stanford University, the equivalent digital gate count in terms of power consumption for a 10-bit ADC at 0.13 um is about 100K, and this number grows almost exponentially for larger ADC and modern advanced nodes.

A new circuit design technique, digitally assisted analog (DAA), delivers a promising solution to address the performance and power challenges to further expand the scope of analog designs to meet today's application requirements. Let's use a simple ADC to explain the concept of DAA:

Figure 1 shows a conventional ADC and Figure 2 shows a DAA style ADC. In Figure 2 a conventional, high performance, power consuming ADC is replaced by a very simple, low-power ADC, followed by a digital post-processor to apply corrections to the output to achieve the same accuracy as the conventional ADC. Compared to the conventional ADC, the DAA ADC has a significant benefit in terms of power and area.

In addition, DAA style designs are easier to port to advanced nodes since majority of the computation task will be performed by the digital post-processor which typically demonstrates an even larger advantage in power, performance and area (PPA) at advanced nodes. With the increasingly wide usage of embedded processors, such as the ARM Cortex-M series, designers can achieve additional benefits in terms of productivity and flexibility thanks to the great software capability of such processors.

The above example just illustrates one specific approach for DAA circuits. In general, in DAA circuits, the assisting digital logic is used to monitor analog performance through the different stages of the operation and to adjust parameters of the analog circuits (such as bias, resistance, capacitance) through calibration loops to meet overall design objectives.

We have seen significant advancements of DAA designs in recent years from the design community, and its proliferation signifies a new era of mixed-signal design. By replacing more and more analog circuitry with digital counterparts to achieve the ever more aggressive PPA targets, we foresee an explosion of new mixed-signal design starts. As a result, the industry is demanding a true mixed-signal design methodology for design, verification and implementation to meet the requirements of such design styles. In the follow-up blogs, we will talk more about how the Cadence mixed-signal solution is best positioned to meet such new mixed-sign design challenges and how you can learn more by joining us at DAC.

Qi Wang

The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react to a Pcell, but Pcell code should not react to, interact with, or be dependent on an environment. Although it is possible to create Pcells dependent on something in your current or local environment, and/or using unsupported or un-recommended functions, Pcell code is likely to fail when you try to translate it for a different environment.

Functions that are not supported for use within SKILL pcells usually belong to specific applications (tools); they are unknown to other environments, to other tools, and to data translators. For example, if you create a Pcell in the Virtuoso environment and include place-and-route functions, the Pcell will fail in the layout environment. Also, application-specific functions that are not supported for customer use can disappear or change, without notice.

Why you should create a Pcell? Creating Pcells for the ECO sometimes helps when we are not sure what size of cell we will have to use for fixing timing violations. Then,  just changing a parameter in the Pcell may do the trick. Generally, you can identify them by their prefixes. However, you can also use all of the basic SKILL language functions. In the following example, we will demonstrate how you can insert the buffer during hold time fix (as part of the ECO) flow using Pcell:

1.   At the Linux prompt set the following environment variables:

setenv CDS_ENABLE_EXP_PCELL true

setenv CDS_EXP_PCELL_DIR ./.expressPcells

 2.    Invoke Virtuoso and open the design. Note that for Virtuoso versions before IC6.1.4.500.1, VLS-XL or VLS-GXL is required to save the express PCell cache. In IC6.1.4.500.1 and later versions, all Virtuoso products support this.

 3.    Select Tools->Express Pcell Manager. Fill out all the details and Enable Caching of the Pcells check box with Auto Save option. Press Save Copy to save the Pcell Layout Cache. This step is necessary to enable inter-operation of the data between Encounter and Virtuoso.

 4.    Open the design using  

Library Manager -> <Library name> <Cell name> <view name>

 5.    Zoom and select the flip-flop (FF1), in front of which the Pcell has to be inserted.

 6.    To placed the Pcell go to create -> Instance -> Library:pcell cell:pcell view:layout and placed the instance (I1) to a specific location (x1, y1) in between the flip-flop (FF1) and previous Instance (I2).

 7.    To do the connectivity

Select I2 instance->connectivity->net->propagate-> A: I2 Y: net1

Select I1 instance->connectivity->net->propagate-> A: net1 Y: net2

Select FF1 Instance->connectivity->net->propagate->D: net2

 8.    Press Save copy to save the design to OA and exit Virtuoso.

 9.    To do ECO routing in the Encounter Digital Implementation System (EDIS), make sure the same environment variables of step 1 is set before invoking the tool.

10. Before restoring the OA design database, update the config file with the Pcell library as below:

set rda_Input(ui_timelib,max) ./lib/max/spcbuf_wc.lib"

set rda_Input(ui_timelib,min) ./lib/min/spcbuf_bc.lib"

 11. Within EDI, follow these steps to restore the OA design.

restoreOaDesign <Library name> <cell name> <view name>

The design, including the Pcells, should now be read in properly.  If the Pcells still do not appear correctly, remove the ./.expressPcells directory and repeat steps 1-4 above. This will make sure new Pcell abstracts are created.

Note: In IC6.1.4 onwards, the cache saved is in a different format than what is saved by IC6.1.3. IC614 can read the Express PCell Cache created by IC6.1.3 and IC6.1.4, but IC6.1.3 cannot read the Express PCell Cache created by IC6.1.4. If you have made a cache using IC6.1.4 then make sure the LD_LIBRARY_PATH environment variable points to <IC6.1.4>/tools/lib while using EDIS. For example:

  setenv LD_LIBRARY_PATH <IC6.1.4>/tools/lib

If the cache was made by IC6.1.3 then the LD_LIBRARY_PATH variable can be set to the tools/lib directory under your IC6.1.3 installation. 

12. Finally, take the following steps to do the hold time fixing and save the design into OA database:

ecoRoute

timeDesign -postRoute -hold

saveOaDesign <Library name> <cell name> <view name1> 

Parag Bhatnagar

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso.

• Why use CPF?

The Common Power Format (CPF) describes the design power intent for the whole flow, including digital implementation in Encounter, custom/analog implementation in Virtuoso Schematic Editor, and further into simulation. In Virtuoso Schematic XL, CPF creates the inherited connections for you in an automated way. You may want to reuse the same CPF that was used for your digital block implementation in Encounter.

• What might CPF contain?
  • Power domains with their shutoff conditions if applicable
  • Power and ground nets
  • Technology for low power: isolation cells, level-shifters (need to be registered as special cell in Virtuoso)
  • Isolation, shifting and retention policy
  • Power modes and analysis views
  • Library sets
  • Global connection

• What does CPF not contain?

CPF is not a command file. It doesn't contain power domain coordinates, power routing details, number of power switches, or implementation details.

• How can I handle the inherited connections ?

Within the Virtuoso IC 6.1.5 release it is possible to describe your low power intent through a CPF file. This posting describes the method according to the use model described above. Further information, including supported CPF commands, is available in the Virtuoso Schematic XL User Guide.

• What are the requirements?

A consistent power intent for the analog and digital parts of your design is required. You could have explicit power pins and implicit net sets and net expressions defined in parallel.  CPF will update or create the net sets and expressions.

All of the power and ground nets (PG nets) in your design should have the signal type Power or Ground. The default signal type is Signal. This might be the case if you take a closer look at your standard cell library. Power and Ground nets are very often defined as type signal. Another requirement is that your standard cell power connection must be described as an inherited connection. Before you start, make sure that the CPF created is verified for correctness using the Cadence Conformal Low Power product.

And as mentioned before, you need Schematics XL to make use of CPF.

Step by Step introduction

• Setup Schematics XL

After Verilog import Open Check - Rules Setup - Inherited Connections and enable the CPF nets error switch.

To verify the signal types choose Options - Check and enable "set Signal Type from Net and Type Registration."

Applying the right signal type

As mentioned above, we need to make sure to set the right signal type. Descend in the hierarchy by double clicking on a symbol until the standard cells occur. Are your PG nets defined as inherited connections, but the signal type is Signal? If so you need to change it. Because your standard cell library usually is set to read only, we need to change the cells in your design using the register API to provide a complete list of all your PG nets (don't miss the std cell PG nets):

ciRegisterNet("power" list("VDD" "vdd" "VDD!" "VDDA" "VDDD" ....) )

ciRegisterNet("ground" list("VSS" "vss" "VSS!" "GND" "gnd" ....) )

Now check if the PG Signal type gets applied correctly:

ciGetNetNames("power") ciGetNetNames("ground")

Finally we use the Check - Hierarchy command to propagate the changes to the schematic. Don't enable save schematics since you may don't have write access to the Library

Shortcut: schHiCheckHier()

• Import the CPF file

Open "File - Import Power Intend" or type schHiAddCPFNetSets() in the CIW command line to open the CPF import form. Library, Cell and View Name are already filled in. The View Name List may be changed by adopting by editing "Options - Check - Views to check.

Specify your CPF File name

Use ‘Register Special Low Power cells' for Isolation cells , Level shifter cells, Power switches, ...Use ‘Remove existing Power Intend' if you are not sure which power is defined and you want to rebuild the power connection. The alternative is to use "Edit - Power Intend - Remove netSet properties." The progress is logged in CIW and CDS.log files.

Again, the last step is to propagate the power intent through the hierarchies and we use "Check - Hierarchy."

• Verify the power intent

After importing and applying the CPF file you may want to verify the created power intent. To verify the created power domains, rules, mappings ... Enable "Window - Assistant - Power Intend Export" for a review.

To verify the created inherited connections on a specific instance open "Edit- Net Expressions - Available properties" and select a block or instance.

If you want to verify the evaluated names from net expressions open "Edit- Net Expressions - Evaluated Names."  In case you want to review which instances are connected to a PG net, use the Search assistant to search for a net and check the User properties.

Kind Regards,

Andreas Lenz 

The new era of “Internet Everywhere” creates a whole new spectrum of applications, ranging from health care, automotive, to entertainment and cloud computing, which demand more and more mixed-signal and low power designs.  In fact, mixed-signal applications have become one of the fastest growing segments in the electronics and semiconductor industry.

Traditional mixed-signal designs treat the analog and digital designs as two independent tasks. It has become clear in recent years that such a design methodology will not be able to meet the challenges of current and future advanced mixed-signal designs. For example, on the verification side, mixed-signal designers are facing increasing difficulties in design and verification of complex mixed-signal SoCs, even though there are continuous improvements in the performance of analog and mixed-signal simulation tools. Without a comprehensive mixed-signal verification methodology, first-silicon success will be in jeopardy, which will in turn hurt the profitability of the companies.

On the implementation side, the technology challenges imposed by advanced nodes and tighter integration between analog circuitry and digital control logic demand that designers adopt a methodology to enable seamless analog and digital co-design to meet tape-out schedules and reduce design costs. Such a methodology change has been talked about in the industry for several years, but until now there has not been a complete reference book to document such methodologies and show how they can revolutionize mixed-signal designs. 

A new book, Mixed-Signal Methodology Guide, will be released by Cadence in this summer and will meet these requirements. The book is co-authored by mixed-signal design experts from Cadence as well as experts from the designer community. Find out more on www.cadence.com/msmguide. A preproduction release of the book will be featured at DAC 2012 in the Cadence booth #1930.

Qi Wang 

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved with for mixed-signal, as well as the latest updates on tools and flows support.

1. Tutorial on Analog and Mixed-Signal Design at Advanced Process Nodes (jointly by TSMC, Freescale, Cadence). Time: Monday June 4^th 8:30 AM - 10:30 AM, repeated at 11:30 AM - 1:30 PM, and again at 3:30 PM - 5:30 PM. Location: 306 (Moscone Convention Center)

2. Luncheon on Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design. Time: Monday June 4^th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)

3. Luncheon on Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs (jointly by ARM, NXP, Cadence). Time: Tuesday June 5^th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)

4. The pre-production release of the industry's first mixed-signal design methodology book, Mixed-Signal Design Methodology Guide. Time: Monday June 4^th - Wednesday June 6^th. Location: Cadence Booth #1930.

5. A demo on applying the latest mixed-signal verification methodology to a design using the Cortex-M0 in an ultra low power application. Time: Monday June 4^th - Wednesday June 6^th. Location: ARM Booth #1414, #802.

6. A floor demo of new tool capabilities to verify low power intent of a mixed-signal design from an analog design environment (Virtuoso) by leveraging digital tool capabilities (Conformal and Encounter). Location: Cadence Booth #1930.

7. Four exciting customer and partner presentations on mixed-signal design in the Cadence EDA360 Theater at Booth 1930:

• Monday June 4^th 2:00PM by TowerJazz on AMS Flow for Power Management Designs. (Also in TowerJazz Booth #1105 throughout the conference.)
• Monday June 4^th 3:00PM by Maxim Integrated on high-performance, low power ADCs designed in Cadence Mixed-Signal Flow
• Monday June 4^th 5:00PM by GlobalFoundries on 28nm Production Ready AMS Reference Flow. (Also in Global Foundries Booth #303 throughout the conference.)
• Tuesday June 5^th 4:00PM by ST on mixed-signal verification

8. Addressing Mixed-Signal Functional Verification Challenges using Virtuoso Multi-Mode Simulation. Time: Monday June 4^th 12:00PM-1:00PM, Tuesday June 5^th 2:00PM-3:00PM, Wednesday June 6^th 9:00AM-10:00AM. Location: Cadence Demo Suite #2 at Booth 1930.

9. Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs. Time: Monday June 4^th 3:00PM-4:00PM, Wednesday June 6^th 4:00PM-5:00PM. Location: Cadence Demo Suite #2 & #3 at Booth 1930.

10. Boosting Productivity and Reducing Turnaround Time with an Integrated Mixed-Signal Physical Implementation Flow. Time: Tuesday June 5^th 9:00AM-10:00AM, Wednesday June 6^th 4:00PM-5:00PM. Location Cadence Demo Suite #2 at Booth 1930.

If you are still confused, there is only one way out - go to the Denali Party by Cadence. I wish everyone a fun time at DAC!

Qi Wang

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed-signal designs. One main objective of this seminar series is to bring the awareness of the need for a design methodology change to the broad mixed-signal designer community worldwide. The event was very successful and you can find some previous blog coverage here:

M/S Technology on Tour Blog - Model Validation and Assertion Based Verification

Is China Ready for Next Generation Mixed-signal Design?

Analog/Mixed-Signal Behavioral Modeling - When to Use What

Recently, Cadenced announced a new series of worldwide Mixed-Signal ToT events. What’s new this time compared to what we delivered one year ago? One major shift in this new series is that we will focus more on how to deploy the new methodologies into real designs, rather than the methodology itself. Many of the methodologies we had been promoting over the past a few years have become more and more mature with support from EDA tools in production.

In fact, Cadence recently announced the pending availability of a Mixed-Signal Methodology Guide later this summer and showcased the preproduction copies at DAC 2012. To demonstrate that some of the mentioned methodologies are ready for deployment for production designs, we will include four tool demos in this seminar. Depending on the availability of R&D presenters and regional requirements, some or all of the following demos will be shown:

• Mixed-signal low power verification demo: CPF aware mixed-signal simulation for designs with power management features, automatic CPF macro model generation for custom or mixed-signal blocks, and application of formal methods for SoC low-power verification.
• ARM Cortex M0 demo: Mixed-signal simulation of a Cortex M0 based fuel tank pressure control system using Verilog-A and wreal models for analog components with software debugging capabilities.
• Architecture level design exploration demo: Using Cadence Incyte Chip Estimator to explore different IPs in a mixed-signal design to make architectural level decisions for best PPA tradeoff.
• Mixed-signal implementation using OpenAccess based interoperability demo: OA based interoperability between Virtuoso and Encounter to enable an integrated physical implementation flow for analog centric mixed-signal designs.

The Mixed-signal ToT starts with a seminar in Taiwan on June 21 and will be expanded to many other different regions worldwide throughout the rest of the year. If you are interested in having the event in your region, please send your request to Kristin@cadence.com.

Qi Wang 

While most of my colleagues in the US were taking a nice break during the July 4^th week, a small group of people including me was on the road for a mixed-signal Tech-on-Tour in China. There was some debate internally on whether designers in China would be interested in such a topic. What we had experienced last week was a clear (not mixed) signal from the IC designer community in China that they are hungry for knowledge in this area, and they want technologies to help them design mixed-signal chips.

The trip was quite hectic, -- 3 cities in a week. It started from Beijing on July 2^nd, then Shanghai on July 4^th and finally Shenzhen on July 6^th. I was particularly worried about the attendance on the first day. The Euro Cup 2012 (Soccer) final game started at 3 am local time, and I know how strong the attraction of this game is for people over there, including myself. I felt relieved when I saw a fully packed seminar room with most attendees arriving on time. I was particularly impressed by the focus and commitment of those attendees, as people were talking notes and asking questions throughout the seminar.

After Beijing, we went on to Shanghai where the designer interest for mixed-signal just blew me away. We had to close our registration site early due to reaching the maximum capacity. The seminar was held in the new Cadence office site in Shanghai within the Kerry Business Center. The training room can accommodate 100 people, but we had more than 120 people come. The room was packed with no standing room! In addition to the great seminar, I was also impressed by the convenience of having many restaurants right below the office. I wish I could have tried them all, but I only had two days there and I had to move to Shenzhen for the last stop of the trip.

The Shenzhen seminar was comparable to the Beijing one in terms of attendance but we had some people came from Hong Kong as well. Overall, the total attendance of the China tour was more than 200 from many different companies. One highlight of this series was the joint presentation with ARM on the use of MCUs in mixed-signal design, and how the Cadence solution makes it easier for designers to design, verify and implement Cortex-M based mixed-signal designs. In fact, the Segment Marketing Manager of ARM in Shanghai, Lifeng Geng, was with us for all three seminars and gave a presentation on embedded processor-based design for mixed-signal applications and the advantages of Cortex-M series from ARM.

We wrapped up the whole series quite smoothly and the team was happy with the turnout. I would have been in a great mood to start a new week except for my miseries on the way back home. I was stuck at the Shenzhen airport for seven hours while waiting for my flight to Shanghai to take off. I felt lucky to arrive in Shanghai in time for the flight to SFO via Tokyo, but the flight from Shanghai to Tokyo was delayed for three hours and the flight from Tokyo to SFO left without me.

Not everything was so bad though. I bumped into Lifeng at the Shenzhen airport as we were both stuck there, even though we were on different flights. We really did not have time to get to know each other at the seminars due to the busy schedule. This incident gave us some good time to chat aboiut technology, work and life, and get to know each other better. I finally got back home on Sunday and I'm thinking about taking the high speed train in China next time.

Qi Wang

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored by Pierluigi Daglio and Marco Carlini from STMicroelectronics that has garnered a lot of interest from the verification community.

Metric-driven verification is the norm for digital designs. But, we can extend this concept to analog/mixed signal designs. Analog/mixed signal verification in the context of full chip verification can achieve a respectable coverage level without compromising on performance levels of digital verification. This can be accomplished by using more robust and abstract analog behavior models such as Real Number (RNM) models using Verilog-AMS wreal as an example. RNM models are also provided in VHDL and System Verilog extensions as well. 

Typically, analog verification is based on detailed transistor level simulations run using SPICE-level simulators in a bottom-up flow. Digital verification is based on a top-down approach and has a uniform verification plan using the Universal Verification Methodology (UVM). This metric driven approach uses coverage-directed random stimulus generation and supports multiple verification languages. However, with the trend towards complex mixed-signal SoCs, analog and digital verification cannot afford to stay isolated from one another.

To address the growing verification challenges in today's mixed signal designs, engineers have been using mixed-signal co-simulation. With this approach, the analog behavior models are modeled using Verilog-AMS or VHDL-AMS languages. Mixed-signal simulators are available to then simulate the analog portion using the analog solver and digital portion using a digital event driven simulation engine. But, this approach has 2 key disadvantages.

• 1. The performance bottleneck of this co-simulation is still governed by slow transistor level analog simulation models. In today's complex digital-centric mixed-signal SoCs, achieving satisfactory coverage level in a reasonable amount of time is an impossible task.
• 2. The expertise required to write efficient analog behavioral model is hard to come by. A badly written behavioral model can cause huge performance degradation.

Newer approaches to using RNM to model continuous analog behavior in discrete digital models are gaining a lot of traction. The wreal language extension in Verilog-AMS offers the best trade-off between performance and accuracy, and thus helps analog designers achieve acceptable coverage levels. This performance gain is achieved by using fast digital simulators like Incisive Enterprise Simulator to replace extremely slow mixed-signal solutions.

In addition to performance gain, RNM models introduce a metric-driven verification approach as well as assertions to analog/ mixed-signal designs. With assertion-based verification, top-level verification coverage levels can be managed to the specifications as desired.

Cadence has further extended wreal beyond the Language Reference Manual limitations for more effective usage, and come up with flow that is unique and efficient. Apart from supporting wreal extensions in its verification offerings, Cadence is now pioneering key technologies that will make the use of RNM adoption easier for the verification teams.

Here are two new methodologies that are needed to accelerate the metric-driven verification approach for mixed signal designs:

• To overcome the inefficiencies in creating models, the process of generating RNM models from schematic design input needs to be automated. This addresses the very important problem of writing RNM models for analog portions.
• A streamlined flow is needed to validate the wreal models against the representative analog design. This automated flow will compare the simulation results from RNM and analog design (transistor-level) and provide pass/fail statistics. Once verified, these RNM models are then qualified to be used in a full chip verification flow.

A typical mixed-signal verification flow using RNM consists of the following:

• Automated RNM model generation from schematics
• Automated RNM model validation using a streamlined approach.
• Metric-driven verification approach using Incisive Enterprise Planner and Verification Cockpit
• Coverage closure and overall verification plan management using Specman/Specman-AMS

To learn more about this topic, please see the following whitepapers:

Solutions for Mixed-Signal SoC Verification

Mixed-Signal Design Challenges and Requirements

You can listen to an audio recording of the STMicroelectronics EDA360 Theater presentation (June 5, 4:00 pm) and view the slides here.

Sathishkumar Balasubramanian

I recently came across a Wall Street Journal article,"ARM Chases Bigger Slice of Smaller Chips,"  that provides a very interesting perspective on how ARM is positioned to capture the microcontroller market, which is its next growth area. ARM based microprocessors are clearly dominating the mobile products from smart phones to tablets across Windows, Android and IOS mobile eco-systems. Most of these devices are using ARM based Cortex A series processors, which provide a very delicate balance between good performance and power efficiency requirements.

However, for ARM, the microcontroller market is still untapped, and this is where ARM is planning its next major push. Before we go any further, I would like to elaborate on what is a micro-controller and how it is differs from Cortex A-series mobile processors that ARM sells for smart phones.

Block diagram of pressure control system

Most of the ARM based smart phones have ARM microprocessors (Cortex A series) along with memory and graphics circuitry to provide the mobile experience. A microcontroller is a single integrated circuit that contains embedded processor cores, memory and programmable I/O peripherals. Usually microcontrollers perform a custom function tailored to specific applications.

For example, a Fuel Gauge pressure sensor's function is to monitor the fuel pressure and level at real time. Typically on average, a automobile will have close to 30 microcontrollers performing various critical functions. Now, you can imagine the size of the MCU market compared to smart phones in terms of numbers alone.

Key characteristics/requirements for a typical micro-controller are reliability, low cost, and extreme low power requirements.

Microcontrollers based on ARM's Cortex-M family satisfy the above requirements and more.  Cortex-M based MCUs are 32 bit wide compared to 8 bit wide micro-controllers available from other vendors.  With 32-bit ARM processors, a microcontroller can process complex instructions in a shorter time and can reduce the on-board flash needed in a 8-bit microcontroller. Also, ARM based microcontroller instruction sets are compatible with ARM based Cortex A series processors, and they fit into ARM's huge ecosystem comprised of 30+ RTOS, Cortex MCO software interface standard (CMSIS), and 10+ tool chains.

Cadence has a long standing collaboration with ARM in design and integration of high performance ARM processors using Cadence's expertise in design tools and methodology.  At the Design Automation Conference this year, Cadence's mixed-signal solutions group showcased a demo which focuses on the integration of ARM Cortex-M processors into mixed-signal applications using the industry leading Virtuoso analog/mixed-signal design environment. Cadence mixed-signal solutions address typical  MCU design challenges like full-chip verification, low power design, and reduced area, and enables first-silicon success.

 Demo system block diagram -- adding analog interface to Cortex-M System Design Kit

The demo models a pressure sensitive Fuel Injection system based on the ARM Cortex M0 based system. It shows how to develop the M0 based system and debug across HW/SW and analog/digital boundaries. It starts with ARM's Cortex-M System Design kit and integrates with AMS and RTL peripherals. Design intent is then verified using system level mixed-signal simulation. Finally, the demo uses the Cadence InCyte Chip Estimator for IP selection and initial floorplan to feed in to the implementation tool for the physical implementation.

If you are planning on developing Cortex-M based processors, this demo will demonstrate how Cadence mixed-signal solutions works well with ARM based processors. The Cortex-M Mixed signal demo is currently available on demand. Please contact your Cadence representative to learn more about the demo and Cadence mixed-signal solutions.

Satishkumar Balasubramanian

Mixed-signal applications are among the fastest growing segments in the electronics and semiconductor industry. Applications in mobile communication, networking, power management, automotive, medical, imaging, safety and security require a very high integration of analog and digital functionality at system, SoC and IP levels.

Unfortunately, compared with the advancement of digital designs over the past decade, the state of art analog design is significantly lagging behind. For example, the throughput of microprocessors doubles every 1.5 years while it takes three times longer to achieve the same advancement for analog designs. Another big roadblock for analog designs is the power consumption. According to Boris Murmann, professor at Stanford University, the equivalent digital gate count in terms of power consumption for a 10-bit ADC at 0.13 um is about 100K, and this number grows almost exponentially for larger ADC and modern advanced nodes.

A new circuit design technique, digitally assisted analog (DAA), delivers a promising solution to address the performance and power challenges to further expand the scope of analog designs to meet today's application requirements. Let's use a simple ADC to explain the concept of DAA:

Figure 1 shows a conventional ADC and Figure 2 shows a DAA style ADC. In Figure 2 a conventional, high performance, power consuming ADC is replaced by a very simple, low-power ADC, followed by a digital post-processor to apply corrections to the output to achieve the same accuracy as the conventional ADC. Compared to the conventional ADC, the DAA ADC has a significant benefit in terms of power and area.

In addition, DAA style designs are easier to port to advanced nodes since majority of the computation task will be performed by the digital post-processor which typically demonstrates an even larger advantage in power, performance and area (PPA) at advanced nodes. With the increasingly wide usage of embedded processors, such as the ARM Cortex-M series, designers can achieve additional benefits in terms of productivity and flexibility thanks to the great software capability of such processors.

The above example just illustrates one specific approach for DAA circuits. In general, in DAA circuits, the assisting digital logic is used to monitor analog performance through the different stages of the operation and to adjust parameters of the analog circuits (such as bias, resistance, capacitance) through calibration loops to meet overall design objectives.

We have seen significant advancements of DAA designs in recent years from the design community, and its proliferation signifies a new era of mixed-signal design. By replacing more and more analog circuitry with digital counterparts to achieve the ever more aggressive PPA targets, we foresee an explosion of new mixed-signal design starts. As a result, the industry is demanding a true mixed-signal design methodology for design, verification and implementation to meet the requirements of such design styles. In the follow-up blogs, we will talk more about how the Cadence mixed-signal solution is best positioned to meet such new mixed-sign design challenges and how you can learn more by joining us at DAC.

Qi Wang

The purpose for creating a Pcell is to automate the creation of data. Pcells should be designed as standalone entities, independent of the environment in which they are created and independent of the variety of environments in which you or someone else might want to use them. An environment can react to a Pcell, but Pcell code should not react to, interact with, or be dependent on an environment. Although it is possible to create Pcells dependent on something in your current or local environment, and/or using unsupported or un-recommended functions, Pcell code is likely to fail when you try to translate it for a different environment.

Functions that are not supported for use within SKILL pcells usually belong to specific applications (tools); they are unknown to other environments, to other tools, and to data translators. For example, if you create a Pcell in the Virtuoso environment and include place-and-route functions, the Pcell will fail in the layout environment. Also, application-specific functions that are not supported for customer use can disappear or change, without notice.

Why you should create a Pcell? Creating Pcells for the ECO sometimes helps when we are not sure what size of cell we will have to use for fixing timing violations. Then,  just changing a parameter in the Pcell may do the trick. Generally, you can identify them by their prefixes. However, you can also use all of the basic SKILL language functions. In the following example, we will demonstrate how you can insert the buffer during hold time fix (as part of the ECO) flow using Pcell:

1.   At the Linux prompt set the following environment variables:

setenv CDS_ENABLE_EXP_PCELL true

setenv CDS_EXP_PCELL_DIR ./.expressPcells

 2.    Invoke Virtuoso and open the design. Note that for Virtuoso versions before IC6.1.4.500.1, VLS-XL or VLS-GXL is required to save the express PCell cache. In IC6.1.4.500.1 and later versions, all Virtuoso products support this.

 3.    Select Tools->Express Pcell Manager. Fill out all the details and Enable Caching of the Pcells check box with Auto Save option. Press Save Copy to save the Pcell Layout Cache. This step is necessary to enable inter-operation of the data between Encounter and Virtuoso.

 4.    Open the design using  

Library Manager -> <Library name> <Cell name> <view name>

 5.    Zoom and select the flip-flop (FF1), in front of which the Pcell has to be inserted.

 6.    To placed the Pcell go to create -> Instance -> Library:pcell cell:pcell view:layout and placed the instance (I1) to a specific location (x1, y1) in between the flip-flop (FF1) and previous Instance (I2).

 7.    To do the connectivity

Select I2 instance->connectivity->net->propagate-> A: I2 Y: net1

Select I1 instance->connectivity->net->propagate-> A: net1 Y: net2

Select FF1 Instance->connectivity->net->propagate->D: net2

 8.    Press Save copy to save the design to OA and exit Virtuoso.

 9.    To do ECO routing in the Encounter Digital Implementation System (EDIS), make sure the same environment variables of step 1 is set before invoking the tool.

10. Before restoring the OA design database, update the config file with the Pcell library as below:

set rda_Input(ui_timelib,max) ./lib/max/spcbuf_wc.lib"

set rda_Input(ui_timelib,min) ./lib/min/spcbuf_bc.lib"

 11. Within EDI, follow these steps to restore the OA design.

restoreOaDesign <Library name> <cell name> <view name>

The design, including the Pcells, should now be read in properly.  If the Pcells still do not appear correctly, remove the ./.expressPcells directory and repeat steps 1-4 above. This will make sure new Pcell abstracts are created.

Note: In IC6.1.4 onwards, the cache saved is in a different format than what is saved by IC6.1.3. IC614 can read the Express PCell Cache created by IC6.1.3 and IC6.1.4, but IC6.1.3 cannot read the Express PCell Cache created by IC6.1.4. If you have made a cache using IC6.1.4 then make sure the LD_LIBRARY_PATH environment variable points to <IC6.1.4>/tools/lib while using EDIS. For example:

  setenv LD_LIBRARY_PATH <IC6.1.4>/tools/lib

If the cache was made by IC6.1.3 then the LD_LIBRARY_PATH variable can be set to the tools/lib directory under your IC6.1.3 installation. 

12. Finally, take the following steps to do the hold time fixing and save the design into OA database:

ecoRoute

timeDesign -postRoute -hold

saveOaDesign <Library name> <cell name> <view name1> 

Parag Bhatnagar

Let's assume you are managing a schematic-driven top level design in Virtuoso and you want to import a digital block Verilog netlist into Virtuoso. This is a very common use model in mixed-signal implementation. While the Layout Database is saved in Open Access (OA), the optimized Verilog netlist needs to be imported into Virtuoso.

• Why use CPF?

The Common Power Format (CPF) describes the design power intent for the whole flow, including digital implementation in Encounter, custom/analog implementation in Virtuoso Schematic Editor, and further into simulation. In Virtuoso Schematic XL, CPF creates the inherited connections for you in an automated way. You may want to reuse the same CPF that was used for your digital block implementation in Encounter.

• What might CPF contain?
  • Power domains with their shutoff conditions if applicable
  • Power and ground nets
  • Technology for low power: isolation cells, level-shifters (need to be registered as special cell in Virtuoso)
  • Isolation, shifting and retention policy
  • Power modes and analysis views
  • Library sets
  • Global connection

• What does CPF not contain?

CPF is not a command file. It doesn't contain power domain coordinates, power routing details, number of power switches, or implementation details.

• How can I handle the inherited connections ?

Within the Virtuoso IC 6.1.5 release it is possible to describe your low power intent through a CPF file. This posting describes the method according to the use model described above. Further information, including supported CPF commands, is available in the Virtuoso Schematic XL User Guide.

• What are the requirements?

A consistent power intent for the analog and digital parts of your design is required. You could have explicit power pins and implicit net sets and net expressions defined in parallel.  CPF will update or create the net sets and expressions.

All of the power and ground nets (PG nets) in your design should have the signal type Power or Ground. The default signal type is Signal. This might be the case if you take a closer look at your standard cell library. Power and Ground nets are very often defined as type signal. Another requirement is that your standard cell power connection must be described as an inherited connection. Before you start, make sure that the CPF created is verified for correctness using the Cadence Conformal Low Power product.

And as mentioned before, you need Schematics XL to make use of CPF.

Step by Step introduction

• Setup Schematics XL

After Verilog import Open Check - Rules Setup - Inherited Connections and enable the CPF nets error switch.

To verify the signal types choose Options - Check and enable "set Signal Type from Net and Type Registration."

Applying the right signal type

As mentioned above, we need to make sure to set the right signal type. Descend in the hierarchy by double clicking on a symbol until the standard cells occur. Are your PG nets defined as inherited connections, but the signal type is Signal? If so you need to change it. Because your standard cell library usually is set to read only, we need to change the cells in your design using the register API to provide a complete list of all your PG nets (don't miss the std cell PG nets):

ciRegisterNet("power" list("VDD" "vdd" "VDD!" "VDDA" "VDDD" ....) )

ciRegisterNet("ground" list("VSS" "vss" "VSS!" "GND" "gnd" ....) )

Now check if the PG Signal type gets applied correctly:

ciGetNetNames("power") ciGetNetNames("ground")

Finally we use the Check - Hierarchy command to propagate the changes to the schematic. Don't enable save schematics since you may don't have write access to the Library

Shortcut: schHiCheckHier()

• Import the CPF file

Open "File - Import Power Intend" or type schHiAddCPFNetSets() in the CIW command line to open the CPF import form. Library, Cell and View Name are already filled in. The View Name List may be changed by adopting by editing "Options - Check - Views to check.

Specify your CPF File name

Use ‘Register Special Low Power cells' for Isolation cells , Level shifter cells, Power switches, ...Use ‘Remove existing Power Intend' if you are not sure which power is defined and you want to rebuild the power connection. The alternative is to use "Edit - Power Intend - Remove netSet properties." The progress is logged in CIW and CDS.log files.

Again, the last step is to propagate the power intent through the hierarchies and we use "Check - Hierarchy."

• Verify the power intent

After importing and applying the CPF file you may want to verify the created power intent. To verify the created power domains, rules, mappings ... Enable "Window - Assistant - Power Intend Export" for a review.

To verify the created inherited connections on a specific instance open "Edit- Net Expressions - Available properties" and select a block or instance.

If you want to verify the evaluated names from net expressions open "Edit- Net Expressions - Evaluated Names."  In case you want to review which instances are connected to a PG net, use the Search assistant to search for a net and check the User properties.

Kind Regards,

Andreas Lenz 

The new era of “Internet Everywhere” creates a whole new spectrum of applications, ranging from health care, automotive, to entertainment and cloud computing, which demand more and more mixed-signal and low power designs.  In fact, mixed-signal applications have become one of the fastest growing segments in the electronics and semiconductor industry.

Traditional mixed-signal designs treat the analog and digital designs as two independent tasks. It has become clear in recent years that such a design methodology will not be able to meet the challenges of current and future advanced mixed-signal designs. For example, on the verification side, mixed-signal designers are facing increasing difficulties in design and verification of complex mixed-signal SoCs, even though there are continuous improvements in the performance of analog and mixed-signal simulation tools. Without a comprehensive mixed-signal verification methodology, first-silicon success will be in jeopardy, which will in turn hurt the profitability of the companies.

On the implementation side, the technology challenges imposed by advanced nodes and tighter integration between analog circuitry and digital control logic demand that designers adopt a methodology to enable seamless analog and digital co-design to meet tape-out schedules and reduce design costs. Such a methodology change has been talked about in the industry for several years, but until now there has not been a complete reference book to document such methodologies and show how they can revolutionize mixed-signal designs. 

A new book, Mixed-Signal Methodology Guide, will be released by Cadence in this summer and will meet these requirements. The book is co-authored by mixed-signal design experts from Cadence as well as experts from the designer community. Find out more on www.cadence.com/msmguide. A preproduction release of the book will be featured at DAC 2012 in the Cadence booth #1930.

Qi Wang 

Analog/mixed-signal design is a hot topic at the Design Automation Conference! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), you can keep up with the latest developments in mixed-signal design methodology, including design, implementation and verification. You will find it is very hard to choose from so many options. Here is a quick guide to presentations, demos and other events Cadence is involved with for mixed-signal, as well as the latest updates on tools and flows support.

1. Tutorial on Analog and Mixed-Signal Design at Advanced Process Nodes (jointly by TSMC, Freescale, Cadence). Time: Monday June 4^th 8:30 AM - 10:30 AM, repeated at 11:30 AM - 1:30 PM, and again at 3:30 PM - 5:30 PM. Location: 306 (Moscone Convention Center)

2. Luncheon on Overcoming Variability and Productivity Challenges in Your High-Performance, Advanced Node, Custom/Analog Design. Time: Monday June 4^th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)

3. Luncheon on Overcoming the Challenges of Embedding Ultra Low-Power, ARM 32-bit Processors into Analog/Mixed-Signal Designs (jointly by ARM, NXP, Cadence). Time: Tuesday June 5^th 11:30AM - 1:00PM. Location: 270-276 (Moscone Convention Center)

4. The pre-production release of the industry's first mixed-signal design methodology book, Mixed-Signal Design Methodology Guide. Time: Monday June 4^th - Wednesday June 6^th. Location: Cadence Booth #1930.

5. A demo on applying the latest mixed-signal verification methodology to a design using the Cortex-M0 in an ultra low power application. Time: Monday June 4^th - Wednesday June 6^th. Location: ARM Booth #1414, #802.

6. A floor demo of new tool capabilities to verify low power intent of a mixed-signal design from an analog design environment (Virtuoso) by leveraging digital tool capabilities (Conformal and Encounter). Location: Cadence Booth #1930.

7. Four exciting customer and partner presentations on mixed-signal design in the Cadence EDA360 Theater at Booth 1930:

• Monday June 4^th 2:00PM by TowerJazz on AMS Flow for Power Management Designs. (Also in TowerJazz Booth #1105 throughout the conference.)
• Monday June 4^th 3:00PM by Maxim Integrated on high-performance, low power ADCs designed in Cadence Mixed-Signal Flow
• Monday June 4^th 5:00PM by GlobalFoundries on 28nm Production Ready AMS Reference Flow. (Also in Global Foundries Booth #303 throughout the conference.)
• Tuesday June 5^th 4:00PM by ST on mixed-signal verification

8. Addressing Mixed-Signal Functional Verification Challenges using Virtuoso Multi-Mode Simulation. Time: Monday June 4^th 12:00PM-1:00PM, Tuesday June 5^th 2:00PM-3:00PM, Wednesday June 6^th 9:00AM-10:00AM. Location: Cadence Demo Suite #2 at Booth 1930.

9. Improving Verification Coverage and Reducing Silicon Re-Spins for Functional and Low-Power Verification of Mixed-Signal Designs. Time: Monday June 4^th 3:00PM-4:00PM, Wednesday June 6^th 4:00PM-5:00PM. Location: Cadence Demo Suite #2 & #3 at Booth 1930.

10. Boosting Productivity and Reducing Turnaround Time with an Integrated Mixed-Signal Physical Implementation Flow. Time: Tuesday June 5^th 9:00AM-10:00AM, Wednesday June 6^th 4:00PM-5:00PM. Location Cadence Demo Suite #2 at Booth 1930.

If you are still confused, there is only one way out - go to the Denali Party by Cadence. I wish everyone a fun time at DAC!

Qi Wang

About a year ago, Cadence offered a worldwide Tech-On-Tour (ToT) series for mixed-signal designs. One main objective of this seminar series is to bring the awareness of the need for a design methodology change to the broad mixed-signal designer community worldwide. The event was very successful and you can find some previous blog coverage here:

M/S Technology on Tour Blog - Model Validation and Assertion Based Verification

Is China Ready for Next Generation Mixed-signal Design?

Analog/Mixed-Signal Behavioral Modeling - When to Use What

Recently, Cadenced announced a new series of worldwide Mixed-Signal ToT events. What’s new this time compared to what we delivered one year ago? One major shift in this new series is that we will focus more on how to deploy the new methodologies into real designs, rather than the methodology itself. Many of the methodologies we had been promoting over the past a few years have become more and more mature with support from EDA tools in production.

In fact, Cadence recently announced the pending availability of a Mixed-Signal Methodology Guide later this summer and showcased the preproduction copies at DAC 2012. To demonstrate that some of the mentioned methodologies are ready for deployment for production designs, we will include four tool demos in this seminar. Depending on the availability of R&D presenters and regional requirements, some or all of the following demos will be shown:

• Mixed-signal low power verification demo: CPF aware mixed-signal simulation for designs with power management features, automatic CPF macro model generation for custom or mixed-signal blocks, and application of formal methods for SoC low-power verification.
• ARM Cortex M0 demo: Mixed-signal simulation of a Cortex M0 based fuel tank pressure control system using Verilog-A and wreal models for analog components with software debugging capabilities.
• Architecture level design exploration demo: Using Cadence Incyte Chip Estimator to explore different IPs in a mixed-signal design to make architectural level decisions for best PPA tradeoff.
• Mixed-signal implementation using OpenAccess based interoperability demo: OA based interoperability between Virtuoso and Encounter to enable an integrated physical implementation flow for analog centric mixed-signal designs.

The Mixed-signal ToT starts with a seminar in Taiwan on June 21 and will be expanded to many other different regions worldwide throughout the rest of the year. If you are interested in having the event in your region, please send your request to Kristin@cadence.com.

Qi Wang 

While most of my colleagues in the US were taking a nice break during the July 4^th week, a small group of people including me was on the road for a mixed-signal Tech-on-Tour in China. There was some debate internally on whether designers in China would be interested in such a topic. What we had experienced last week was a clear (not mixed) signal from the IC designer community in China that they are hungry for knowledge in this area, and they want technologies to help them design mixed-signal chips.

The trip was quite hectic, -- 3 cities in a week. It started from Beijing on July 2^nd, then Shanghai on July 4^th and finally Shenzhen on July 6^th. I was particularly worried about the attendance on the first day. The Euro Cup 2012 (Soccer) final game started at 3 am local time, and I know how strong the attraction of this game is for people over there, including myself. I felt relieved when I saw a fully packed seminar room with most attendees arriving on time. I was particularly impressed by the focus and commitment of those attendees, as people were talking notes and asking questions throughout the seminar.

After Beijing, we went on to Shanghai where the designer interest for mixed-signal just blew me away. We had to close our registration site early due to reaching the maximum capacity. The seminar was held in the new Cadence office site in Shanghai within the Kerry Business Center. The training room can accommodate 100 people, but we had more than 120 people come. The room was packed with no standing room! In addition to the great seminar, I was also impressed by the convenience of having many restaurants right below the office. I wish I could have tried them all, but I only had two days there and I had to move to Shenzhen for the last stop of the trip.

The Shenzhen seminar was comparable to the Beijing one in terms of attendance but we had some people came from Hong Kong as well. Overall, the total attendance of the China tour was more than 200 from many different companies. One highlight of this series was the joint presentation with ARM on the use of MCUs in mixed-signal design, and how the Cadence solution makes it easier for designers to design, verify and implement Cortex-M based mixed-signal designs. In fact, the Segment Marketing Manager of ARM in Shanghai, Lifeng Geng, was with us for all three seminars and gave a presentation on embedded processor-based design for mixed-signal applications and the advantages of Cortex-M series from ARM.

We wrapped up the whole series quite smoothly and the team was happy with the turnout. I would have been in a great mood to start a new week except for my miseries on the way back home. I was stuck at the Shenzhen airport for seven hours while waiting for my flight to Shanghai to take off. I felt lucky to arrive in Shanghai in time for the flight to SFO via Tokyo, but the flight from Shanghai to Tokyo was delayed for three hours and the flight from Tokyo to SFO left without me.

Not everything was so bad though. I bumped into Lifeng at the Shenzhen airport as we were both stuck there, even though we were on different flights. We really did not have time to get to know each other at the seminars due to the busy schedule. This incident gave us some good time to chat aboiut technology, work and life, and get to know each other better. I finally got back home on Sunday and I'm thinking about taking the high speed train in China next time.

Qi Wang

Even though it's been over 2 months since this year's Design Automation Conference in San Francisco, I am still surprised by the response that metric-driven, mixed-signal verification gets from our design community. Cadence had quite a few customer presentations at the EDA360 Theater at DAC this year. However, there was one presentation titled "Metric Driven Verification Approach for Analog/Mixed Signal IPs" authored by Pierluigi Daglio and Marco Carlini from STMicroelectronics that has garnered a lot of interest from the verification community.

Metric-driven verification is the norm for digital designs. But, we can extend this concept to analog/mixed signal designs. Analog/mixed signal verification in the context of full chip verification can achieve a respectable coverage level without compromising on performance levels of digital verification. This can be accomplished by using more robust and abstract analog behavior models such as Real Number (RNM) models using Verilog-AMS wreal as an example. RNM models are also provided in VHDL and System Verilog extensions as well. 

Typically, analog verification is based on detailed transistor level simulations run using SPICE-level simulators in a bottom-up flow. Digital verification is based on a top-down approach and has a uniform verification plan using the Universal Verification Methodology (UVM). This metric driven approach uses coverage-directed random stimulus generation and supports multiple verification languages. However, with the trend towards complex mixed-signal SoCs, analog and digital verification cannot afford to stay isolated from one another.

To address the growing verification challenges in today's mixed signal designs, engineers have been using mixed-signal co-simulation. With this approach, the analog behavior models are modeled using Verilog-AMS or VHDL-AMS languages. Mixed-signal simulators are available to then simulate the analog portion using the analog solver and digital portion using a digital event driven simulation engine. But, this approach has 2 key disadvantages.

• 1. The performance bottleneck of this co-simulation is still governed by slow transistor level analog simulation models. In today's complex digital-centric mixed-signal SoCs, achieving satisfactory coverage level in a reasonable amount of time is an impossible task.
• 2. The expertise required to write efficient analog behavioral model is hard to come by. A badly written behavioral model can cause huge performance degradation.

Newer approaches to using RNM to model continuous analog behavior in discrete digital models are gaining a lot of traction. The wreal language extension in Verilog-AMS offers the best trade-off between performance and accuracy, and thus helps analog designers achieve acceptable coverage levels. This performance gain is achieved by using fast digital simulators like Incisive Enterprise Simulator to replace extremely slow mixed-signal solutions.

In addition to performance gain, RNM models introduce a metric-driven verification approach as well as assertions to analog/ mixed-signal designs. With assertion-based verification, top-level verification coverage levels can be managed to the specifications as desired.

Cadence has further extended wreal beyond the Language Reference Manual limitations for more effective usage, and come up with flow that is unique and efficient. Apart from supporting wreal extensions in its verification offerings, Cadence is now pioneering key technologies that will make the use of RNM adoption easier for the verification teams.

Here are two new methodologies that are needed to accelerate the metric-driven verification approach for mixed signal designs:

• To overcome the inefficiencies in creating models, the process of generating RNM models from schematic design input needs to be automated. This addresses the very important problem of writing RNM models for analog portions.
• A streamlined flow is needed to validate the wreal models against the representative analog design. This automated flow will compare the simulation results from RNM and analog design (transistor-level) and provide pass/fail statistics. Once verified, these RNM models are then qualified to be used in a full chip verification flow.

A typical mixed-signal verification flow using RNM consists of the following:

• Automated RNM model generation from schematics
• Automated RNM model validation using a streamlined approach.
• Metric-driven verification approach using Incisive Enterprise Planner and Verification Cockpit
• Coverage closure and overall verification plan management using Specman/Specman-AMS

To learn more about this topic, please see the following whitepapers:

Solutions for Mixed-Signal SoC Verification

Mixed-Signal Design Challenges and Requirements

You can listen to an audio recording of the STMicroelectronics EDA360 Theater presentation (June 5, 4:00 pm) and view the slides here.

Sathishkumar Balasubramanian