Clik here to view.
Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional...
What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent. It’s now made...
View ArticleClik here to view.
Start Your Engines: Automatic Configuration Creation for a Mixed-Signal Test...
In this post, I will cover how you can easily create an automatic configuration for a mixed-signal test bench.(read more)
View ArticleClik here to view.
Start Your Engines: Win Le Mans with the SimVision Mixed-Signal Debug Option
In this post, I will explain how the new Cadence SimVision Mixed-Signal Debug option can reveal the Invisible portions of an Analog and Mixed-Signal Test Benches.(read more)
View ArticleClik here to view.
Start Your Engines: Seven Habits of Highly Efficient Mixed Signal...
This blog shares insights on the seven best practices that should be followed by mixed-signal verification engineers. (read more)
View ArticleClik here to view.
Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional...
What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent. It’s now made...
View ArticleClik here to view.
Start Your Engines: Using CLIPS to Generate Portable Virtuoso IP for SoC...
Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the...
View ArticleClik here to view.
Start Your Engines: The Blog-o-Meter Check
A summary of the blogs published in the Start Your Engines blog series.(read more)
View ArticleClik here to view.
Start Your Engines: Seamlessly Reusing Advanced Digital Testbenches in AMS UNL
The Virtuoso Advanced Testbench Reuse flow with Xcelium eases the painful process of SV UVM testbench reuse in the AMS UNL flow. Continue reading to know more.(read more)
View ArticleClik here to view.
Start Your Engines: Modeling Current-Based Port Connections between...
In a mixed-signal simulation, the electrical signal modules and real number modeling (RNM) modules mostly have voltage-based ports. However, there may be still a few ports that need to model the...
View ArticleClik here to view.
Start Your Engines: The Why and How of Generating Spectre Netlists for Analog...
Read to know about generating netlist in the Spectre native format using AMS UNL.(read more)
View ArticleClik here to view.
Start Your Engines: Modeling Current-Based Port Connections between...
In a mixed-signal simulation, the electrical signal modules and real number modeling (RNM) modules mostly have voltage-based ports. However, there may be still a few ports that need to model the...
View ArticleClik here to view.
Start Your Engines: AMS Flex – Our Next Generation Architecture Matures
An AMS Designer Flex simulation gives you the most immediate access to the latest simulation technology on either side, gets out of the way of the core engines and allows the engine performance to...
View ArticleClik here to view.
Start Your Engines: An Innovative and Efficient Approach to Debug Interface...
This blog introduces you to an efficient way to debug interface elements or connect modules in a mixed-signal simulation.(read more)
View ArticleClik here to view.
Virtuosity: Reliability Analysis Report-Reliable Results Made Interactive
Read through this blog to know more about the new Reliability Report view in Virtuoso ADE Assembler and Virtuoso ADE Explorer.(read more)
View ArticleClik here to view.
Virtuoso Meets Maxwell: Getting Your Existing SiP File Into Virtuoso RF Solution
I have been involved in the Virtuoso RF Solution for the last four years. Most of the customers I work with have a SiP package already in progress. They often ask "How do I get my SiP design into...
View ArticleClik here to view.
Spectre Tech Tips: Accuracy 101
In this post, we will learn about the most important parameters for the analog simulators that affect the accuracy of the simulation results. We will also understand how each parameter limits the...
View ArticleClik here to view.
Clik here to view.
Virtuoso ICADVM20.1 ISR26 and IC6.1.8 ISR26 Now Available
The ICADVM20.1 ISR26 and IC6.1.8 ISR26 production releases are now available for download.(read more)
View ArticleClik here to view.
Spectre Tech Tips: Introducing Spectre X EMIR Voltus-XFi
This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides support to the Voltus-XFi Custom Power Integrity Solution.(read more)
View ArticleClik here to view.
Virtuosity: Custom IC Design Flow/Methodology - Circuit Physical Verification...
Read this blog for an overview to the Circuit physical verification and parasitic extraction design stage in the Custom IC Design methodology and the key design steps which can help you achieve...
View Article