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Verifying Power Intent in Analog and Mixed-Signal Designs Using Formal Methods
Analog and Mixed-signal (AMS) designs are increasingly using active power management to minimize power consumption. Typical mixed-signal design uses several power domains and operate in a dozen or more...
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OpenAccess (OA) Based Flow - Efficient Implementation of Mixed-Signal Design...
I had the great opportunity to represent Cadence at the Design Automation Conference (DAC) at Austin a few weeks back. In my role as a Mixed-Signal Solutions evangelist at Cadence, I was thoroughly...
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Coming Soon: Asia-Pacific Mixed Signal Summit and Tech-On-Tour Events
Cadence is bringing the Analog/Mixed-Signal Summit to Shenzhen, China, and the Mixed-Signal/Low-Power Focused Technology-On-Tours to Penang and Singapore later in July 2013. Cadence will showcase...
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Cadence’s Annual Mixed-Signal Summit 2013: A Mind Meld of Mixed-Signal Design...
If you're a fan of the Star Trek series (my six-year-old son and I watch it together faithfully!), you know the Vulcan Mind Meld. (If you're not a Trekkie, the mind-meld is a process of transferring...
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IC6.1.6 Virtuoso Space-Based Mixed-Signal Router (VSR)
Virtuoso Space-Based Router (VSR) is routing solution integrated into the Virtuoso Layout Suite, which provides a comprehensive set of routing features for a variety of layout tasks. One major design...
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Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL
Why is There a Need for Low Power Solutions?With an increase in the demand for high-performance, multi-tasking systems-on-chips (SoCs) for communication and computing, the power requirements for these...
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Start Your Engines: AMSD Flex—Take your Pick!
Introduction to AMSD Flex mode and its benefits.(read more)
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Start Your Engines: AMSD Flex – Your Instant Access to Latest Spectre Features!
This blog talks about how to enable the AMS Designer flex mode.(read more)
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Start Your Engines: The Why and How of Generating Spectre Netlists for Analog...
Read to know about generating netlist in the Spectre native format using AMS UNL.(read more)
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Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL
Why is There a Need for Low Power Solutions?With an increase in the demand for high-performance, multi-tasking systems-on-chips (SoCs) for communication and computing, the power requirements for these...
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How Can You Learn About Mixed-Signal Verification and Implementation Flows at...
The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on...
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It’s Late, But the Party is Just Getting Started
Key Findings: Many more chip programs are crossing the tipping point and need advanced mixed-signal verification methodologies and technologies. A deterministic march to closure is needed. The Cadence...
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The Elephant in the Room: Mixed-Signal Models
Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but...
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Start Your Engines: Exporting AMS UNL IP for Reuse in the Digital Functional...
What if there existed a seamless way to pass verified design blocks freely between the analog and digital verification teams, all the while, retaining the domain originator’s IP intent. It’s now made...
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Start Your Engines: Using CLIPS to Generate Portable Virtuoso IP for SoC...
Mixed-signal functional verification is a complex task and it takes a lot of effort and multiple simulation cycles to verify a design correctly. A mixed-signal verification engineer works with the...
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Start Your Engines: The Blog-O-Meter Check
A summary of the blogs published in the Start Your Engines blog series.(read more)
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Top 5 Issues that Make Things Go Wrong in Mixed-Signal Verification
Key Findings: There are a host of issues that arise in mixed-signal verification. As discussed in earlier blogs, the industry trends indicate that teams need to prepare themselves for a more mixed...
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How Can You Learn About Mixed-Signal Verification and Implementation Flows at...
The vast majority of SoCs today are advanced mixed-signal designs. The old mixed-signal world looked like an analog environment on the left bolted to a digital environment on the right. Depending on...
View ArticleClik here to view.
It’s Late, But the Party is Just Getting Started
Key Findings: Many more chip programs are crossing the tipping point and need advanced mixed-signal verification methodologies and technologies. A deterministic march to closure is needed. The Cadence...
View ArticleClik here to view.
The Elephant in the Room: Mixed-Signal Models
Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but...
View Article